[share_ebook] Design of Cost-Efficient Interconnect Processing Units: Spidergon STNoC (System-on-Chip Design and Technologies)

Description

• Author: Marcello Coppola
• Publisher: CRC
• Publish Date: September 17, 2008
• ISBN: 1420044710
• Pages: 288

• Hardcover: 288 pages
• Publisher: CRC; 1 edition (September 17, 2008)
• Language: English
• ISBN-10: 1420044710
• ISBN-13: 978-1420044713

 

Product Description
Written by leading experts in the field, Design of Cost-Efficient Interconnect Processing Units: Spidergon STNoC comprehensively examines the current state-of-the-art and future trends in multiprocessor system-on-chip (MPSoC), in particular network-on-chip (NoC) design. Incorporating simple methods with easy-to-understand examples, this book considers a wealth of important theoretical and practical topics, such as technological deep sub-micron effects, generic NoC components, topological properties, embeddings of common communication patterns, and system-level design. A complementary CD-ROM features a practical NoC training approach based on the award-winning OCCN environment. 

About the Author
STMicroelectronics, Grenoble, France ISD SA, Heraklion, Greece STMicroelectronics, Grenoble Cedex, France Savant Company Inc, Irvine, California, USA

 

http://rapidshare.com/files/195886084/CRC.Design.of.Cost.Efficient.Interconnect.Processing.Units.Spidergon.STNoC.Sep.2008.pdf

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