[request_ebook] System-On-Chip Test Architectures : Nanometer Design for Testability

Description

The same book is also published under the Morgan Kaufmann imprint. This book is a new book which deals with VLSI system-on-chip testing.

 Taken from amazon.com:

Modern electronics testing has a legacy of more than 40 years. The introduction of new technologies, especially nanometer technologies with 90nm or smaller geometry, has allowed the semiconductor industry to keep pace with the increased performance-capacity demands from consumers. As a result, semiconductor test costs have been growing steadily and typically amount to 40% of today?s overall product cost.

This book is a comprehensive guide to new VLSI Testing and Design-for-Testability techniques that will allow students, researchers, DFT practitioners, and VLSI designers to master quickly System-on-Chip Test architectures, for test debug and diagnosis of digital, memory, and analog/mixed-signal designs.

KEY FEATURES
* Emphasizes VLSI Test principles and Design for Testability architectures, with numerous illustrations/examples.
* Most up-to-date coverage available, including Fault Tolerance, Low-Power Testing, Defect and Error Tolerance, Network-on-Chip (NOC) Testing, Software-Based Self-Testing, FPGA Testing, MEMS Testing, and System-In-Package (SIP) Testing, which are not yet available in any testing book.
* Covers the entire spectrum of VLSI testing and DFT architectures, from digital and analog, to memory circuits, and fault diagnosis and self-repair from digital to memory circuits.
* Discusses future nanotechnology test trends and challenges facing the nanometer design era; promising nanotechnology test techniques, including Quantum-Dots, Cellular Automata, Carbon-Nanotubes, and Hybrid Semiconductor/Nanowire/Molecular Computing.
* Practical problems at the end of each chapter for students.

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1. Ebooks list page : 1543
2. VLSI Test Principles and Architectures: Design for Testability
3. [request_ebook] System-On-A-Chip: Design and Test
4. System-on-Chip Test Architectures (Systems on Silicon)
5. System-on-Chip Test Architectures (Systems on Silicon)
6. System-on-Chip Test Architectures (Systems on Silicon)
7. System-Level Modeling and Design Space Exploration for Multiprocessor Embedded System-on-Chip Architectures
8. System-on-a-Chip: Design and Test
9. System-on-a-Chip: Design and Test
10. System-On-A-Chip Design and Test
11. On-Chip Communication Architectures: System on Chip Interconnect (Systems on Silicon) (Systems on Silicon)
12. Network-on-Chip Architectures: A Holistic Design Exploration
13. [share_ebook] Network-on-Chip Architectures: A Holistic Design Exploration
14. Full-Chip Nanometer Routing Techniques
15. [share_ebook] Design of Cost-Efficient Interconnect Processing Units: Spidergon STNoC (System-on-Chip Design and Technologies)
16. Design of System on a Chip