System-on-a-Chip Verification - Methodology and Techniques

Description

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System-on-a-Chip Verification - Methodology and Techniques

 

By Prakash Rashinkar, Peter Paterson, Leena Singh,

Publisher:   Springer
Number Of Pages:   392
Publication Date:   2000-12-31
Sales Rank:   1235350
ISBN / ASIN:   0792372794
EAN:   9780792372790
Binding:   Hardcover
Manufacturer:   Springer
Studio:   Springer
Average Rating:   3

System-On-a-Chip Verification: Methodology and Techniques is the first book to cover verification strategies and methodologies for SOC verification from system level verification to the design sign- off. The topics covered include Introduction to the SOC design and verification aspects, System level verification in brief, Block level verification, Analog/mixed signal simulation, Simulation, HW/SW Co-verification, Static netlist verification, Physical verification, and Design sign-off in brief. All the verification aspects are illustrated with a single reference design for Bluetooth application. System-On-a-Chip Verification: Methodology and Techniques takes a systematic approach that covers the following aspects of verification strategy in each chapter: Explanation of the objective involved in performing verification after a given design step; Features of options available; When to use a particular option; How to select an option; and Limitations of the option. This exciting new book will be of interest to all designers and test professionals.

Review:

DIGITAL System on a Chip, Not ANALOG

This may be the world's most complete over view of digital system-on-a-chip verification. I don't know.

I was excited to find a book on this subject, because this is a specialized subject not covered well by the publishing industry, because this is a subject that is very difficult to write about, with only perhaps a few tens of thousands of active specialists, and because of these quotations from the book's back cover "[fully covers] system on a chip," "Bluetooth because it addresses reality," "comprehensive guide to overall SOC verification," "authors... leave no stone unturned in this comprehensive overview of [chip verification] tools and methodolgies."

Now that I have received the book, I feel that it is important to make note of what I know this book is not. It is not a book with any significant coverage of analog.

I am an analog chip designer that has 24 years experience, a good part of that time spent verifying my analog and mixed-signal designs. This book has a single 24 page chapter on analog, "Analog/Mixed-Signal Simulation," which taught me nothing. The chapter lists and defines the standard specialized nomenclature of the analog verification software, gives an example simple VerilogA behavioral model for a crude resistor-transresistor DAC, and gives a crude behavioral test example. I think that most all stones are left unturned for analog or mixed-signal chip verification. The authors mention SPICE, spectre, and Cadence Analog Design Environment only. I just finished a 37000 transistor analog & mixed-signal chip verification, and this book mentioned none of the tools and methods that I used, which included Mentor's Modeltech Modelsim and Synopsys's Saber. The examples are of value in giving existing digital chip verification experts an example of how to get started with a crude VerilogA behavioural modeling of analog blocks to be fit into a digital chip verification flow.

All of the authors are or were associated with Cadence Design Systems, according to the book. They write "The [EDA software] industry has been slow in responding to the mixed-signal design and simulation requirements." "Analog engineers have been using [SPICE] for analog simulation for over 30 years..." "The third VSIA verification meeting concluded 'verification is not just very hard, it is very, very hard.'" I agree, but there is still much left to write about. I congratulate them on being some of the first to attempt such a writing task.

 

Review:

Poor examples explanation

I am not an expert in this field but what I learn are just some simple concepts. It takes some pages on the bluetooth SOC design
example with fractional C code. There is no structure about the examples and its hard to understand what the authors will explain(actually, I just feel ??what??)

http://rapidshare.com/files/62093982/system_on_a_chip_verfication_methodology_and_techniques.pdf

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