VHDL Coding Styles and Methodologies

Description

This text follows up the first edition of the same book and also “VHDL Answers to Frequently Asked Questions”, first and second editions. The book was originally written as a teaching tool for a VHDL training course. This new edition provides practical information on reusable software methodologies for the design of bus functional models for testbenches. It also provides guidelines in the use of VHDL for synthesis. All VHDL code described in the book is on a companion CD, which also includes the GNU toolsite with EMACS language-sensitive editor (with VHDL, Verilog, and other language templates), and TSHELL tools that emulate a Unix shell. Model Technology included an evaluation version of ModelSim, a recognized industry standard VHDL/Verilog compiler and simulator that supports easy viewing of the models under analysis, along with many debug features. The text is intended for professional engineers as well as students. It is organized in 13 chapters, each covering a separate aspect of the language, with complete examples. It provides a practical approach to learning VHDL. Combining methodologies and coding styles, along with VHDL rules, the text aims to lead the reader in the right direction from the beginning. Included is a CD that contains: all code included in the book; GNU EMACS language-sensitive editor with VHDL, Verilog, and templates for other languages; GNU TSHELL tools that emulate Unix shell; 30-day evaluation of ModelSim VHDL compiler/simulator from Model Technology; 20-day evaluation of Synplify VHDL/Verilog FPGA synthesizer from Synplicity; VHDL template demonstrating the language syntax; and VHDL ‘87 and HDL ‘93 formal syntax in HTML format.

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