VHDL Prentice Hall - Verilog HDL - A Guide To Digital Design And Synthesis

Description

1-1 Typical Design Flow

2-1 Top-down Design Methodology
2-2 Bottom-up Design Methodology
2-3 Ripple Carry Counter
2-4 T-flipflop
2-5 Design Hierarchy
2-6 Stimulus Block Instantiates Design Block
2-7 Stimulus and Design Blocks Instantiated in a Dummy Top-Level Module
2-8 Stimulus and Output Waveforms

3-1 Example of Nets

4-1 Components of a Verilog Module
4-2 SR Latch
4-3 I/O Ports for Top and Full Adder
4-4 Port Connection Rules
4-5 Design Hierarchy for SR Latch Simulation

5-1 Basic Gates
5-2 Buf and Not Gates

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