Writing Testbenches: Functional Verification of HDL Models, Second Edition

Description

ASICs, systems-on-a-chip (SoC), boards and entire systems.

Topics included in the new Second Edition:
*Discussions on OpenVera and e;
*Approaches for writing constrainable random stimulus generators;
*Strategies for making testbenches self-checking;
*A clear blueprint of a verification process that aims for first time success;
*Recent advances in functional verification such as coverage-driven verification process;
*VHDL and Verilog language semantics;
*The semantics are presented in new verification-oriented languages;
*Techniques for applying stimulus and monitoring the response of a design;
*Behavioral modeling using non-synthesizeable constructs and coding style;
*Updated for Verilog 2001.

http://rapidshare.com/files/19751679/_Kluwer__Writing_Testbenches–Functional_Verification_of_HDL_Models.pdf.html

http://tinyurl.com/39q5vq

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